• 专利附录
  • 专利说明
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  • 类似技术
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    • 专利摘要:
    The invention relates to a circuit (3) for controlling a first field effect transistor (M) of a power converter, intended for a converter comprising at least a first and a second transistor in series between two terminals. applying a first voltage (VH), said circuit comprising a circuit (4) for detecting the opening of the second transistor.
    公开号:FR3013916A1
    申请号:FR1361689
    申请日:2013-11-27
    公开日:2015-05-29
    发明作者:Romain Grezaud；Francois Ayel；Jean-Christophe Charles Crebier；Nicolas Rouger
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] B12721 - DD14420ST 1 CONTROL CIRCUIT FOR POWER CONVERTER Field This description relates generally to electronic circuits, more particularly to the field of power converters and, more particularly, to the production of a control circuit for a power converter. BACKGROUND OF THE PRIOR ART Power converters are widely used in the electronics industry.
    [0002] The present description relates more particularly to power supplies comprising, between two terminals for applying an input voltage of continuous power or not, two switches in series, the midpoint of which is generally connected to an inductive element constituting, for example, the inductor. the output filter, the primary of a transformer, the inductance of an electric motor ... The presence of at least two switches in series between two power supply terminals requires a control avoiding simultaneous conduction of these two switches . These switches generally consist of field effect transistors, most commonly MOS transistors, JFETs or very high mobility field effect transistors (HEMTs).
    [0003] B12721 - DD14420ST 2 This leads to providing, between the respective conduction periods of the transistors, "dead times" during which the two transistors are blocked. During these "dead times", the gate-source voltage is lower than the threshold voltage of the transistor and a current flows in reverse either through the internal diode of one of the transistors if it has one, or through its channel. or by an external diode connected in antiparallel. In all cases, the passage of this current in reverse at these times generates undesired losses. It is therefore generally sought to reduce the dead time during which the two power switches are blocked. Various solutions have already been proposed to reduce this dead time. In particular, since the switching speed varies according to the operating point of the converter and the temperature, it is sought to make this dead time self-adaptive so that it is as short as possible while maintaining protection against short circuit. These solutions are, however, poorly suited to power converters whose switching transistors 20 are powered by a relatively high voltage (greater than 20V), or to power converters whose control circuits for switching switches consist of solid-state transistors. field effect. SUMMARY An embodiment of the present disclosure is to provide a control circuit for a power converter that overcomes all or some of the disadvantages of conventional circuits. An embodiment of the present description is aimed more particularly at a solution adapted to any power circuit, for example a power converter, whose switching switches consist of field effect transistors (whether or not they are realized). in the same technology) with or without internal parasitic diode between drain and source, in series between two terminals for applying a voltage B12721 - DD14420ST 3 power, and controlled by control circuits also consisting of transistors to field effect (realized or not in the same technology). Another embodiment more particularly relates to a solution for automatically adapting the dead time of simultaneous blocking of the power switches, compatible with the terminals usually accessible in an input stage of a power converter. Thus, an embodiment provides a control circuit for a first field effect transistor of a power converter, intended for a converter comprising at least a first and a second transistor in series between two application terminals. a first voltage, said circuit comprising a circuit for detecting the opening of the second transistor. According to one embodiment, the circuit, comprising: an output terminal intended to be connected to the gate of the first transistor; and an input terminal for connection to the source of the first transistor. According to one embodiment, the circuit comprises two control transistors in series between two power supply supply terminals referenced with respect to the potential present on said input terminal. According to one embodiment, a first supply voltage is positive or zero with respect to said potential, the second supply voltage being negative or zero with respect to said potential of the input terminal. According to one embodiment, the detection circuit 30 comprises at least one stage comprising a current mirror formed by two MOS transistors, one of whose transistor has its source connected to an application terminal of the second supply voltage, the other transistor having its source connected to the output terminal of the control circuit.
    [0004] According to one embodiment, the circuit comprises a control terminal intended to receive a control signal in closing or opening of the first transistor and selection between two modes of operation.
    [0005] According to one embodiment, the circuit comprises a combination logic block of said control signal and at least one signal provided by said detection circuit. According to one embodiment, a first operating mode is activated before the opening of the second transistor 10 to enable the detection of this opening. One embodiment also provides a power converter comprising at least a first and a second transistor, in series between two application terminals of a first voltage, in which the first and second transistors 15 are each controlled by a circuit such that above. According to one embodiment: a first control circuit of the first transistor whose input terminal is connected to one of said terminals for applying the DC voltage; and a second control circuit of the second transistor whose input terminal is connected to the midpoint of the series association of the first and second transistors. According to one embodiment, the circuit further comprises a circuit for supplying the control signals of the first and second transistors. An embodiment also provides a method of controlling a converter, wherein a variation of the drain-source voltage is detected at the gate of each transistor. BRIEF DESCRIPTION OF THE DRAWINGS These and other features and advantages will be set forth in detail in the following description of particular embodiments in a non-limiting manner with reference to the accompanying drawings of which: B12721 - DD14420ST FIG. a schematic representation, in the form of blocks, of an example of a power converter equipped with an embodiment of a control circuit of the switches of its input stage; Figure 2 is a more detailed representation of an embodiment of a portion of the control circuit of Figure 1; FIG. 3 schematically and partially shows a part of the control circuit of FIG. 2; FIGS. 4A and 4B partially show elements of the circuit of FIG. 3, applied to the control circuit of one of the switches of the input stage of the converter, and illustrate two operating configurations; FIGS. aA and 5B partially show elements of FIG. 3, applied to the control circuit of the other of the switches of the input stage of the converter, and illustrate two operating configurations; FIGS. 6A, 6B, 6C, 6D, 6E, 6F, 6G and 6H illustrate, in the form of timing diagrams, a mode of operation of the power converter in the configuration of FIG. 4B; FIGS. 7A, 7B, 7C, 7D, 7E, 7F, 7G and 7H illustrate, in the form of timing diagrams, a mode of operation of the power converter in the configuration of FIG. 5B; FIGS. 8A, 8B, 8C, 8D, 8E, 8F, 8G and 8H illustrate, in the form of timing diagrams, another mode of operation of the power converter in the configuration of FIG. 4B; FIGS. 9A, 9B, 9C, 9D, 9E, 9F, 9G and 9H illustrate, in the form of timing diagrams, another mode of operation of the power converter in the configuration of FIG. 5B; B12721 - DD14420ST 6 Figure 10 schematically shows a detailed embodiment of a variant of a detection circuit of the circuit of Figure 2; and FIG. 11 is a block diagram illustrating an example of architecture applied in FIG. 1. Detailed description The same elements have been designated with the same references in the various figures. For the sake of clarity, only the elements useful for understanding the embodiments which will be described have been shown and will be detailed. In particular, the power converter has only been illustrated by its input stage, the described embodiments being compatible with the usual implementations of switching-type power converters or any circuit using at least two switches. between two terminals for applying a voltage. In addition, the generation of the supply voltage of the converter has not been detailed, the described embodiments being again compatible with the usual applications. FIG. 1 very schematically shows in the form of blocks an embodiment of a control circuit 1 for controlling an input stage 22 of a power converter 2 of the switched-mode power supply type. The input stage 22 comprises at least two field effect transistors M2 and M1, in series between two terminals 23 and 24 for applying a supply voltage (power input voltage), in this case. example of a positive voltage VH with respect to the mass. The power input voltage may be approximately constant at the switching frequency scale of transistors M1 and M2, but may be variable at a lower frequency (for example, the 50 Hz frequency of the network). In the arbitrary example of FIG. 1, the midpoint 25 between the transistors M2 and M1 is connected to an inductive element L whose other electrode defines a terminal 26 connected to a fixed potential depending on the application, for example , the B12721 - DD14420ST 7 mass. The inductive element L is symbolized with its series resistance R. This inductive element constitutes, for example, the primary of a transformer 27 whose secondary is symbolized by an inductive element Ls, connected to a circuit 28 comprising the secondary of the switching power supply. This is an example and the embodiments that will be described apply, regardless of the nature of the elements connected downstream or coupled to the inductive element L. In the example of FIG. connected terminal 26 to block 28 to make it stand out that it is connected to the rest of the application. The structure illustrated in FIG. 1 is commonly referred to as a half-bridge converter. In such a converter, the transistors M1 and M2 are alternately controlled to supply energy to the inductive element L. Each transistor M1, M2 is controlled by a circuit 31, respectively 32, consisting of field effect transistors providing, on a terminal 321, respectively 322, a control signal at its gate. A particular case is considered in which the circuits 31 and 32 have similar structures. To simplify the description which follows and unless otherwise specified, the elements of the control circuit assigned to the transistor M1 of the low half-stage will be identified with an index "1", and with an index "2" the elements of the control circuit assigned to the M2 transistor of the upper half-stage, and we will mention these elements without index when referring without distinction to the two circuits. Each circuit 3 (CTRL) comprises a terminal 34 intended to be connected to the source of the transistor M which it controls, therefore to the node 25 for the circuit 32 and to the terminal 24 for the circuit 31. Each circuit 3 is powered by a voltage applied between two terminals 36 and 38. The potential of the terminal 34 is an intermediate potential. In other words, each circuit 3 receives a positive or zero voltage V + with respect to its terminal 34 and a negative or zero voltage V- with respect to its terminal 34. These voltages, referenced with respect to terminal 34 B12721 - DD14420ST 8 which corresponds to the source of the transistor M concerned, are on the one hand related to the need to block the transistors M1 and M2 with voltages lower than their threshold voltages Vth to avoid the risk of parasitic conduction which could otherwise occur following variations of the supply potentials, and secondly related to the need to turn the M1 and M2 transistors with voltages higher than their threshold voltages. In the usual way, the circuits 3 control the transistors M1 and M2 so that they have alternating phases of conduction. For this, each circuit receives, on a terminal 30, a control signal IN coming from a circuit symbolized by a block 5 in FIG. 1, typically controlling the switching periods of the power input voltage Vg according to the needs of the charge. Block 5 receives information representative of the needs of the load on one or more FB inputs. The generation of the signals IN takes into account a need to avoid simultaneous conduction of the transistors M1 and M2 which would short-circuit the supply terminals 23 and 24.
    [0006] However, during the blocking of one of the transistors M (M1 or M2), before conduction of the other (M2, respectively M1), the dead time necessary to avoid simultaneous conduction generates losses related to the conduction of a reverse current in a transistor, due to a gate-source voltage lower than its threshold voltage. The amplitude of this phenomenon can be reduced by rapidly conducting the other transistor (M2, respectively MI) to reduce this reverse conduction time. This amounts to reducing the time out. However, this requires an auto-adaptation of the dead time between the conduction periods of the two transistors M1 and M2 because their switching speeds (turn-on time and blocking time) depend inter alia on the switched operating point and the temperature. .
    [0007] B12721 - DD14420ST 9 It is expected to detect, at the gate of each transistor M, so the terminal 32 of the corresponding circuit 3, the opening of the other transistor M and exploit this detection at the same circuit 3 to turn back the transistor M considered. Thus, as soon as the control circuit 3 of the transistor M1, respectively M2, detects the opening of the other transistor M2, respectively M1, it causes the closing of the transistor M1, respectively M2. This automatically reduces the dead time, so the losses. The dead time is therefore no longer generated in a fixed manner by the remote control block 5 but in a self-adaptive manner and locally by the circuits 3 (CTRL). According to this embodiment, the circuits 31 and 32 are not connected to each other in order to communicate to each other the state in which the transistor they drive is respectively located. This high voltage information is directly recovered by each circuit 3 at the gate, the low voltage side, the transistor that it controls, thus eliminating the need for high voltage components or an additional isolation device. FIG. 2 schematically shows in the form of blocks an embodiment of a circuit 3. For simplicity, the circuits 31 and 32 of the transistors M1 and M2 are structurally identical. They differ in that they are connected to a different transistor and, optionally, by voltages V + and V- which feed them different. Each circuit 3 comprises an amplifier 31 (DRIVER) controlled by logic signals DET and IN. The signal IN 30 corresponds to the conduction control signal of the transistor in question, from the circuit 5 which uses information relating to the needs of the load. The DET signal is a detection signal. IN and DET signals will be detailed later. The amplifier 31 is powered by the supply voltages V + and V- of the circuit 3 (terminals 36 and 38).
    [0008] B12721 - DD14420ST 10 The terminal 34 is connected to a reference terminal 33, common to the voltages V + and V-. The circuit 3 further comprises a detection circuit 4 (DETECT), an embodiment of which will be described later and whose role is to provide a DET information relating to the switching of the other transistor M2 or M1 than that associated with the circuit 3. considered. Circuit 4 is powered by voltages V + and V-. FIG. 3 represents, in more detail, an exemplary embodiment of the amplifier 31. The latter comprises an input stage 312 formed of a logic circuit, for example a D flip-flop, whose role is to combine the states respective signals IN and DET to select the state of an output stage 314. The circuit 312 is powered by the voltages V + and V- and thus provides a signal whose high state is at the level V + and whose state bottom is at V- level (neglecting the voltage drops in the on-state transistors of circuit 312). In the example of FIG. 3, the input D of the flip-flop 312 receives the voltage V +, its clock input receives the signal DET, its reset input R receives the inverse of the signal IN (inverter 313). The circuit 312 provides the result of the combination on the gate of a first transistor P of an output stage 314 of the circuit 31. This output stage 314 comprises two P-channel transistors P and N N-channel, in series between the two terminals 36 and 38 of application of potentials V + and V-. The gate of transistor N receives directly the inverted IN signal. The midpoint of this series association defines the output terminal 32 of the circuit 3, intended to be connected to the gate of the transistor M concerned. When the signal IN goes high, the transistor P remains blocked until the opening of the other transistor M is detected, the signal DET goes high, thus validating the signal IN and therefore closing the transistor M considered. When the signal IN goes low, the transistors P and N become simultaneously and instantaneously blocked. A so-called monitoring phase is provided in which the two P and N transistors are blocked. This phase is triggered by a switching of the signal IN to the high state, caused by the circuit 5, before or simultaneously with the blocking of the transistor M of the other stage by switching its signal IN corresponding to the low state. This monitoring phase ends when the blocking of the other transistor M is detected and the DET signal goes high. When opening the transistor M1 or M2, if the current in the inductive element L is positive, respectively negative, it forces the reverse flow in the transistor M1, respectively M2. For a current in the inductive element L of any sign when the transistor M1, respectively M2, opens, the potential at node 25 varies and the presence of parasitic gate-drain capacitances Cgd and gate-source Cgs of the transistors M is that a current flows not only through the drain-source capacitance Cds, but also at the gate of the other transistor M2, respectively M1 through the gate-drain capacitor Cgd. The circuit 32, respectively 31, is then in a monitoring phase (its signal IN is in the high state and its signal DET is still at the low level), which places the output stage 314 in a high state. impedance (P and N transistors blocked). The circuit 42, respectively 41, can then detect this parasitic current which informs the opening of the transistor M1, respectively M2. The detection of this current by the circuit 42, respectively 41, 30 forces the signal DET12, respectively DET21, to the high state. One embodiment of the detection circuit 4 will be described hereinafter with reference to FIG. 10. For the moment, it is sufficient to note that this circuit detects the presence of a current in the gate of the transistor M, whereas It is in a locked state.
    [0009] B12721 - DD14420ST 12 The direction of the parasitic current during the opening of the transistor Ml, respectively M2, in the parasitic capacitances of the transistor M2, respectively M1, in the open state, depends on the direction of variation of the potential which depends on the direction current flow in the inductive element L (Figure 1). FIGS. 4A and 4B show, in part, the elements of FIG. 3 to illustrate the operation of the circuit 32 at the opening of the transistor M1 while the current in the inductive element is positive and therefore flows from the node 25 to the node 26 Figure 4A illustrates the polarization of transistors P2 and N2 in normal operation. FIG. 4B illustrates the polarization of transistors P2 and N2 in monitoring mode. For the following, neglected voltage drops in the on state in the different transistors, including those of the detector 4 and the logic circuit 312. In normal operation, in the example of Figure 4A where the it is assumed that the transistor M2 is open, the respective gates of the transistors P2 and N2 are brought to the positive potential V2 +. The transistor P2 is thus blocked and the transistor N2 is conducting. At the opening of the transistor M1, a negative parasitic current Igd2 flows through the gate-drain capacitor Cgd2 of the transistor M2 (from the drain to the gate), the transistor N2, the voltage source V2- to reach the transistor M1 (no visible in Figure 4A) and evacuate parasitic charges. When the signal IN2 goes high, the circuit 32 is placed in the monitoring mode, represented by FIG. 4B, as long as the signal DET supplied by the circuit 42 is in the low state. In this mode of operation, the circuit 312 directly applies the inverse of the signal IN2 (thus a low state) to the transistor N2 while maintaining the high level applied to the gate of the transistor P2 until the switching detection of the transistor M1 marking the end of this mode. Therefore, in monitoring mode, the two transistors N2 and P2 constituting the output stage 3142 of the circuit 32 are off, the stage 3142 is in high impedance. At the blocking of the transistor M1, the parasitic current B12721 - DD14420ST 13 then flows from the drain to the source of the transistor M2 by its gate-drain capacitances Cgd2 and gate-source Cgs2. In the case of Figure 4A, the passage of negative parasitic current Igd2 has virtually no impact on the shape of the gate voltage of the transistor M2. In the case of FIG. 4B, the negative gate-drain current can no longer pass through the transistor N2 to reach the potential V2- (its parasite source-drain diode is reverse biased). Therefore, the capacitances Cgs2 and Cgd2 form a capacitive divider bridge and the gate-source capacitance charges and increases the gate potential value by an amount dependent on the magnitude of the variation of the potential at node 25 and the values of the capacitors. capacities Cgd2 and Cgs2. In fact, at the opening of the transistor M1, it can be considered, in the case of a field effect transistor M1 without a diode between drain and source, that the variation of the gate voltage Vgs2 is equal to dVgs2 = (Vth1-Vgs1 ) .Cgd2 / (Cgs2 + Cgd2), where Vth1 represents the threshold voltage of the transistor M1. In the case of a transistor M1 with an antiparallel diode (internal or not), the variation of the gate voltage Vgs2 is dVgs2 = Vf1.Cgd2 / (Cgs2 + Cgd2), where Vf1 represents the voltage drop across the diode during the passage of the current in reverse. It is expected to detect this variation dVgs2 of the gate voltage of the transistor M2 due to the particular monitoring mode to detect the opening of the transistor M1.
    [0010] This operation is similar on the circuit 31 side at the opening of the transistor M2 while the current in the inductive element L is negative flowing from the node 26 to the node 25. FIGS. AA and 5B show, in part, the elements of the FIG. 3 to illustrate the operation of the circuit 31 at the opening of the transistor M2 while the current in the inductive element is positive and flows from the node 25 to the node 26. Figure aA illustrates the polarization of the transistors P1 and N1 in normal operation. FIG. 5B illustrates the polarization of transistors P1 and N1 in monitoring mode.
    [0011] In normal operation, in the example of FIG. 5A, where it is assumed that the transistor M1 is open, the respective gates of the transistors P1 and N1 are brought to the positive potential V1 +. Transistor P1 is therefore blocked and transistor N1 is on. At the opening of the transistor M2, a positive parasitic current Igd1 flows through the gate-drain capacitor Cgd1 of the transistor M1 (from the gate to the drain), the transistor N1, the voltage source V1- to reach the transistor M2 and evacuate parasitic charges.
    [0012] When the signal IN1 goes high, the circuit 31 is placed in monitoring mode, shown in FIG. 5B, as long as the signal DET supplied by the circuit 41 is in the low state. In this operating mode, the circuit 312 directly applies the inverse of the signal IN1 (thus a low state) to the transistor N1 while it maintains the high level applied to the gate of the transistor P1 until the switching detection of the transistor M2 marking the end of this mode. Therefore, in monitoring mode, the two transistors N1 and P1 constituting the output stage 3141 of the circuit 31 are blocked, the stage 3141 is in high impedance. During the blocking of the transistor M2, the induced parasitic positive current Igd1 then passes through the transistor N1 in reverse conduction and the gate to the drain of the transistor M1 by its gate-drain capacitor Cgd1. In the case of Figure aA, the passage of the positive parasitic current Igd1 has virtually no impact on the shape of the gate voltage of the transistor M1. In the case of FIG. 5B, the positive gate-drain current no longer passes through a transistor N1 that is correctly closed in order to reach the node 25. This current always goes in reverse by the transistor N1 whose gate-source voltage is this time lower than its threshold voltage Vth2. Circulation of this current therefore induces a negative variation dVgs1 of the gate voltage of the transistor M1 equal to the voltage drop Vfm across the component N1 leading the parasitic current Igd1 inversely below the threshold. It is intended to detect B12721 - DD14420ST 15 this variation dVgs1 due to the particular mode of monitoring to detect the opening of the transistor M2. This operation is similar, on the circuit side 32, to the opening of the transistor M1 while the current in the inductive element L is negative flowing from the node 26 to the node 25. FIGS. 6A, 6B, 6C, 6D, 6E, 6F 6G and 6H illustrate, in the form of timing diagrams, an example of operation of the circuit in the configuration of FIG. 4B, that is to say of detection of the opening of the transistor M1 by means of the monitoring mode. Figures 6A. at 6H respectively show examples of flows of the current IL in the inductance L by assuming a current flow from the node 25 to the node 26, the drain current Id2 in the transistor M2, the drain current Id1 in the transistor M1 , of the potential LX of the node 25, the states of the signals IN2 and DET12 where DET12 denotes the detection signal supplied by the circuit 42 of the circuit 32, the gate-source voltage Vgs2 of the transistor M2, the states of the signals IN 'and DET21 where DET21 denotes the detection signal supplied by the circuit 41 of the circuit 31, and the gate-source voltage Vgs1 of the transistor M1. Subsequently, one places oneself in the arbitrary case where the transistors M1 and M2 are field effect transistors of the same technology and without parasitic internal diode in antiparallel. The voltages V1 + and V1-, respectively V2 + and V2-, are quite far from the threshold voltage Vth1, respectively Vth2, so that the transistor M1, respectively M2, has both a good conducting state and good condition. blocked. An initial state (instant t60) is assumed in which transistor M1 is on and transistor M2 is off. A current (positive) flows in the inductor L (Figure 6A). The transistor M2 is blocked, its drain current Id2 is zero (Figure 6B) or a negligible level (low compared to the current flowing through the transistor in the on state). A current 35 (negative) flows in the drain of the transistor M1 to the state B12721 - DD14420ST 16 passing (Figure 6C). The voltage LX at node 25 is approximately zero (FIG. 6D). The signal DET12 (FIG. 6E), supplied by the circuit 32, indicating the state of the transistor M1, is in the low state (V2-). The monitoring mode is deactivated (signal IN2 in the low state (V2-)). The gate-source voltage Vgs2 (FIG. 6F) of the transistor M2 is in the low state V2-, lower than its threshold voltage (Vth2) while that Vgs1 (FIG. 6H) of the transistor Ml is in the high state V1 +. The signal IN1 is in the high state (FIG. 6H) and the signal DET21 is in the low state.
    [0013] At a time t61, the circuit 5 causes a switching of the circuit 32 in monitoring mode by switching the signal IN2 to the high state while the signal DET12 to the low state. This switching at the time t61 is caused by the circuit 5, typically before the blocking of the transistor M1 but it can also take place at the same time or after. At a time t62, the transistor M1 receives an opening command by switching the signal IN1 to the low state (FIG. 6G), causing a drop in its gate-source voltage (FIG. 6H) until it reaches the level V1. -. When this voltage becomes lower than its threshold voltage Vth1 (time t63), the transistor M1 is blocked. This causes a drop in the voltage LX to a negative value Vgs1-Vth1 (conduction of the reverse current below the threshold of the transistor M1 without freewheel diode) reached at a time t64. Between instants t63 and t64, the variation of the potential of the node 25 causes the gate-source voltage Vgs2 of the transistor M2 to increase by the parasitic current flowing in its gate-source capacitance Cgs2 (see FIG. 4B). It is assumed that this variation is detected by the circuit 42 at a time t65, later than the instant t64. The signal DET12 then goes high. This information is received by the logic circuit 3122 of the control circuit 3 of the transistor M2, which causes the monitoring mode to stop. From this moment, it is certain that the transistor M1 is open and the transistor M2 can be closed. The logic circuit 3122 then closes the transistor P2 which causes the gate-source voltage of the transistor M2 to grow and causes it to close at a time t66 (FIG. 6F), where a drain current Id2 occurs while that of the transistor M1 disappears and voltage LX begins to grow until potential VII is approximately reached. At a time t65 ', depending on the constitution of the circuit 42, and provided that it is later than the instant t65 and prior to the switching of the signal IN2 to the low state (not visible in the figures) the signal DET12 switches from again to the low state. FIGS. 7A, 7B, 7C, 7D, 7E, 7F, 7G and 7H show the signals of FIG. 6A. at 6H and illustrate an example of operation of the circuit in the configuration of Figure 5B. As for FIGS. 6A to 6H, it is assumed that the current IL in the inductance L is positive and flows from the node 25 to the node 26. An initial state (instant t70) corresponding to the final state of FIGS. 6H. At a time t71, the circuit 5 causes a switching of the circuit 31 in monitoring mode by switching the signal IN 'to the high state while the signal DET21 is in the low state. This switching at time t71 is caused by the circuit 5, typically before the blocking of the transistor M2, but it can also take place at the same instant or after.
    [0014] The opening command of the transistor M2 at time t72 (switching to the low state of the signal IN2) causes a drop in its gate-source voltage (FIG. 7F) to the level V2-. When this gate-source voltage Vgs2 becomes lower than its threshold voltage Vth2 (time t73), the transistor M2 is blocked.
    [0015] This causes the cancellation of the current Id2 in the drain of the transistor M2, the conduction of the current in reverse by the transistor M1 and a drop of the voltage LX to the negative value Vgs1-Vth1 it reaches at a time t74. Between times t73 and t74, the variation of the potential of node 25 causes the gate-source voltage Vgs1 of transistor M1 to decrease by the parasitic current flowing in its gate-source capacitance Cgs1 (see FIG. 5B) and in FIG. output stage 3141 of the circuit 31. It is assumed that this variation is detected by the circuit 41, at a time t75, causing the signal DET21 to go high. This information is received by the logic circuit 3121 of the control circuit 31 of the transistor M1 which immediately stops the monitoring mode. From this moment, it is certain that the transistor M2 is open and that the transistor M1 can be closed. The logic circuit 3121 then closes the transistor P1 which increases the gate-source voltage of the transistor M1 and causes it to close at a time t76 (FIG. 7H), where the voltage LX begins to increase until reaching a low value, corresponding to the product of the drain-source resistance in the state of the transistor passing through the current flowing through it. For simplicity, this value is neglected and Figure 7H shows a cancellation of the voltage LX. At a time t75 ', later than the instant t75, the signal DET21 switches back to the low state. FIGS. 8A, 8B, 8C, 8D, 8E, 8F, 8G and 8H are timing diagrams to be compared with FIGS. 7A to 7H and illustrate the detection, by the circuit 31, of the opening of transistor M2 while the current in FIG. the inductance L is negative flowing from the node 26 to the node 25. The operation is deduced from that illustrated by FIGS. 7A to 7H considering a negative IL current. The instants were referenced t80, t81, t82, t83, t84, t85, t85 'and t86. FIGS. 9A, 9B, 9C, 9D, 9E, 9F, 9G and 9H are timing diagrams to be compared with FIGS. 6A to 6H and illustrate the detection, by the circuit 32, of the opening of transistor M1 while the current in FIG. the inductance L is negative flowing from the node 26 to the node 25. The operation is deduced from that illustrated in Figures 6A to 6G considering a negative current IL. The times were referenced t90, t91, t92, t93, t94, t95, t95 'and t96.
    [0016] B12721 - DD14420ST 19 FIG. 10 represents an exemplary embodiment of a circuit 41 for detecting the gate-drain current in the transistor M1. Figure 10 takes the example of the circuit 41 assigned to the transistor M1 but the mounting for the transistor M2 is similar, only the connections of the inputs / outputs change. Circuit 4 consists of a positive Igd current detector 42, a negative Igd current detector 44. The circuit 42 comprises two N-channel MOS transistors N3 and N4 whose gates are interconnected. The transistor N3 is connected, by its drain, to the terminal 361 for applying the potential V1 + by a current source 421 and, by its source, directly to the terminal 381. The transistor N4 is connected, on the drain side, to the terminal 361 by a resistor 422 and source side directly to the terminal 32. A capacitive element Cl connects gate and source of the transistor N3 whose gate and drain are interconnected. The midpoint between the transistor N4 and the resistor 422 provides a signal DET2in indicating the switching of the transistor M2 for a negative current IL.
    [0017] When the transistor M2 opens, the current Igd1 flows through the parasitic diode of the transistor N1 (see Figure 5B). The potential of the terminal 32, therefore of the source of the transistor N4, decreases while its gate remains at the same potential under the effect of the capacitance Cl. The gate-source voltage of the transistor N4 thus starts to increase at the same time as the gate-source voltage of the transistor M1 decreases. The imbalance generated at the current mirror increases the current in the branch of the transistor N4 which is no longer limited by the value set by the current source 421.
    [0018] This then causes switching of the drain of the transistor N4 which switches from a level approximately equal to V1 + to a level approximately equal to V1- (equivalent of switching from time t75 to Figure 7G). The circuit 44 for detecting a negative Igd current 35 operates according to the same principle and comprises two transistors B12721 - DD14420ST 20 N5 and N6 mounted in current mirrors, the drain of the transistor N5 being connected by a current source to the terminal 361 Its source is connected to the terminal 32. On the transistor side N6, its drain is connected by a resistor 422 to the terminal 361 and its source is connected directly to the terminal 38. The gates of the transistors N5 and N6 are interconnected to the drain of the transistor N5 and connected by a capacitive element C2 to the terminal 32. The midpoint between the resistor 422 and the transistor N6 provides a signal DET2ip indicating the switching of the transistor M2 when the current IL is positive (time t85, Figure 8G). In an assembly of the type of that of Figure 1, one can be satisfied with a detector 42 on the transistor side M2 and a detector 44 on the transistor side M1 insofar as the flow direction of the currents is known.
    [0019] FIG. 11 represents an example of general architecture detailing FIG. 1. A circuit 4 is assigned to each transistor M1 and M2. The two circuits 4 of FIG. 11 may be different from each other and provide signals DET12 and DET21 based either on a negative parasitic current detector 44 (FIG. 10) or on a positive current detector 42 (FIG. 10). However, the two circuits 4 of FIG. 11 may also be similar and be based on a positive and negative parasitic current detector 42 and 44 (FIG. 10) working in parallel.
    [0020] In the preceding figures, the voltages V1 + and V1- are referenced differently from the voltages V2 + and V2-. The voltages V + and V- of each circuit may, however, be identical. An advantage of the embodiments described is that it is now possible to shorten the dead time between the switching of the switching transistors of a power converter. Another advantage is that the circuit is autonomous and does not require any external control signal. In addition, it does not require any high voltage component or additional isolation device. This embodiment is easily usable with conventional control circuit architectures B12721 - DD14420ST 21 using field effect transistor technology and is compatible with any field effect switching transistor. Various embodiments have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, the practical implementation of the converter control circuit described above is within the abilities of those skilled in the art from the given functional indications. In particular, any practical embodiment of a switch associated with the proposed control circuit for detecting a voltage variation between the high voltage terminals (drain and source) of the transistor M at its gate in a low voltage domain thanks to the particular mode of monitoring and detectors of parasitic current is deduced from the functional description of the circuit 3 coupled to the transistor M. Moreover, the realization of the logical combination of the signals IN and DET with usual logic gates is deduced from the functional description of the desired states in output of circuits 312 and can therefore vary from the example of Figure 3. In addition, the choice of voltage levels and values to give the components depends on the application. Similarly, the choice of switching transistor technologies and control circuit transistors depends on the application.
    权利要求:
    Claims (12)
    [0001]
    REVENDICATIONS1. Circuit (3) for controlling a first field effect transistor (M1, M2) of a power converter for a converter having at least said first and a second transistor in series between two terminals (23, 24) applying a first voltage (VH), said circuit comprising a circuit (4) for detecting the opening of the second transistor.
    [0002]
    2. Circuit according to claim 1, comprising an output terminal (32) intended to be connected to the gate of the first transistor (M1, M2); and an input terminal (34) for connection to the source of the first transistor.
    [0003]
    3. Circuit according to claim 2, comprising two control transistors (P, N) in series between two terminals (36, 38) for applying supply voltages (V +, V-) referenced with respect to the potential present on said input terminal (34).
    [0004]
    4. Circuit according to claim 3, wherein a first supply voltage (V +) is positive or zero with respect to said potential, the second supply voltage (V-) being negative or zero with respect to said potential of the terminal d. entrance (34).
    [0005]
    5. Circuit according to claim 4, wherein the detection circuit (4) comprises at least one stage (42, 44) comprising a current mirror formed of two MOS transistors (N3, N4, N5, N6) including a transistor ( N3, N6) has its source connected to an application terminal of the second supply voltage, the other transistor (N4, N5) having its source connected to the output terminal (32) of the control circuit.
    [0006]
    6. Circuit according to any one of claims 1 to 5, comprising a control terminal for receiving a control signal (IN) closing or opening the first transistor (M1, M2) and selection between two operating modes. .B12721 - DD14420ST 23
    [0007]
    7. Circuit according to claim 6, comprising a logic block (312) combining said control signal (IN) and at least one signal (DET) provided by said detection circuit (4).
    [0008]
    8. Circuit according to claim 6 or 7, wherein a first operating mode is activated before the opening of the second transistor (M2, M1) to allow the detection of this opening.
    [0009]
    9. Power converter comprising at least a first (M1) and a second transistor (M2), in series between two terminals (23, 24) for applying a first voltage (VH), in which the first and second transistors are each controlled by a circuit (31, 32) according to any one of the preceding claims.
    [0010]
    The converter according to claim 9, wherein: a first control circuit (31) of the first transistor (M1) having an input terminal (341) connected to one of said DC voltage terminals (24) ; and a second control circuit (32) of the second transistor (M2) having an input terminal (342) connected to the midpoint (25) of the series connection of the first and second transistors.
    [0011]
    11. The converter of claim 10, as appended to any one of claims 6 to 8, further comprising a circuit (5) for providing the control signals (IN ', IN2) of the first (M1) and second (M2) transistors.
    [0012]
    12. The method of controlling a converter according to claim 11, comprising a step of detecting, on the gate of each transistor, a variation of the drain-source voltage of this transistor.
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    同族专利:
    公开号 | 公开日
    EP3075067B1|2017-09-06|
    US20160254750A1|2016-09-01|
    FR3013916B1|2017-05-26|
    WO2015078973A1|2015-06-04|
    EP3075067A1|2016-10-05|
    US9876425B2|2018-01-23|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US5929665A|1997-04-22|1999-07-27|Kabushiki Kaisha Toshiba|Power converter with voltage drive switching device monitored by device parameters and electric parameters|
    US20040041619A1|2002-06-06|2004-03-04|International Recitifier Corporation|Mosgate driver integrated circuit with adaptive dead time|
    US20060164867A1|2003-06-21|2006-07-27|Koninklijke Philips Electronics N.V.|Dead time control in a switching circuit|
    US20070085589A1|2005-09-29|2007-04-19|Kabushiki Kaisha Toshiba|Semiconductor device|
    FR1361689A|1963-07-01|1964-05-22|Voest Ag|Method and apparatus for the continuous manufacture of a zig-zag lattice, and lightweight constructions containing such a lattice|
    IT1308711B1|1999-02-17|2002-01-10|St Microelectronics Srl|SWITCHING DEVICE WITH TWO HALF-BRIDGE AND HALF SWITCHES TO KEEP EACH SWITCH IN INTERDICTION WHEN THE OTHER|
    JP5298679B2|2008-07-17|2013-09-25|サンケン電気株式会社|Resonant switching power supply device and dead time adjustment method thereof|
    CN101944845B|2010-08-06|2012-09-05|东南大学|Switch-level circuit with adaptive control of dead time|
    US8729914B2|2010-11-10|2014-05-20|Infineon Technologies Ag|Detection of the conduction state of an RC-IGBT|
    US8471600B2|2011-09-30|2013-06-25|Infineon Technologies Ag|Detection of the zero crossing of the load current in a semiconductor device|
    US9166469B2|2012-08-29|2015-10-20|Eaton Corporation|System for optimizing switching dead-time and method of making same|US20150365084A1|2014-06-13|2015-12-17|Infineon Technologies Austria Ag|Circuits and methods for operating a circuit|
    US10530360B2|2016-02-29|2020-01-07|Infineon Technologies Austria Ag|Double gate transistor device and method of operating|
    US10276681B2|2016-02-29|2019-04-30|Infineon Technologies Austria Ag|Double gate transistor device and method of operating|
    US9812963B1|2016-05-20|2017-11-07|Monolithic Power Systems, Inc.|Current detection and averaging circuit for switching power supplies with a half-bridge switch circuit topology|
    EP3503365B1|2017-12-22|2020-06-10|GE Energy Power Conversion Technology Limited|Method and device for controlling mosfet switching modules|
    DE102018200707A1|2018-01-17|2019-07-18|Bayerische Motoren Werke Aktiengesellschaft|Method for minimizing switching losses of semiconductor switches of a switching bridge of a power module for a motor vehicle, control device, power module and motor vehicle|
    法律状态:
    2015-11-25| PLFP| Fee payment|Year of fee payment: 3 |
    2016-11-30| PLFP| Fee payment|Year of fee payment: 4 |
    2018-08-31| ST| Notification of lapse|Effective date: 20180731 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1361689A|FR3013916B1|2013-11-27|2013-11-27|CONTROL CIRCUIT FOR POWER CONVERTER|FR1361689A| FR3013916B1|2013-11-27|2013-11-27|CONTROL CIRCUIT FOR POWER CONVERTER|
    PCT/EP2014/075828| WO2015078973A1|2013-11-27|2014-11-27|Control circuit for power converter|
    US15/037,033| US9876425B2|2013-11-27|2014-11-27|Control circuit for power converter|
    EP14802920.0A| EP3075067B1|2013-11-27|2014-11-27|Control circuit for power converter|
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